The present invention relates to generating a delay for a clock signal of a data signal/clock signal pair; and more specifically, relates to introducing a delay to a clock signal of a data signal/clock signal pair within an interconnect cable connecting a first printed circuit board to a second printed circuit board.
In computer systems, in is often necessary to interconnect or xe2x80x9clinkxe2x80x9d electrical components or integrated circuits located on separate printed circuit boards. Most often, a pipelined data bus facilitates passing data and its associated synchronous clock signal through an interconnect cable between printed circuit boards. To maximize performance, especially in high frequency bus link applications, it is important to precisely generate a clock delay in the clock signal relative to the associated data signal in order to ensure that the data is stable at the receiving data capture latch during the clock transition at the receiving integrated circuit. If a delay is not introduced into the clock signal, the data signal and clock signal, a memory device electrically connected to the receiving integrated circuit may capture unstable data, which has an overall detrimental effect on the computer system. In order to provide a stable data signal, it is necessary to maximize both the data set up time and the data hold time for the memory device at the receiving ends.
There are several prior art solutions for introducing a delay within a clock signal. Prior art solutions traditionally generate the clock delay using discrete delay-line components or by adding length to the clock trace (etch) in the printed circuit boards. However, these prior solutions have corresponding disadvantages which make these solutions undesirable.
Board trace impedance and propagation speed tolerances are effected by over/under trace etching during the fabrication process and by printed circuit board dielectric material variations. In addition, deviations from the desired trace impedance may produce signal reflections which degrade timing and noise margins. In addition, variations in propagation speed affect timing margins.
Delay-line components used for providing the clock delay relative to its associated data is undesirous in that the delay-line components are mounted to the outside of a printed circuit board requiring exit vias and mounting pads in the printed circuit board. In addition, delay line components also produce parasitic capacitive and inductive effects on timing and noise margins. For fast edge-rate clocks, either delay-line components or additional trace etches in the printed circuit board can have significant high frequency signal attenuation effects due to dielectric loss and xe2x80x9cskin-lossxe2x80x9d effects in the conductor, thus degrading the clock edge-rate and amplitude.
Further, trace etch delays are frequency dependent. If the frequency of the computer system is later changed or altered, trace etch delays within a printed circuit board no longer provide the desired delay necessary to properly capture stable data at the receiving printed circuit board. Therefore, the printed circuit board must be redesigned and replaced, which is an expensive procedure.
Therefore, there is a need for a connection scheme which will simply and efficiently provides a clock delay relative to an associated data signal. The clock delay must be designed in such a manner than the clock delay can be modified or revised due to a system frequency change in an efficient and reliable manner. In addition, the clock delay must not be effected by the fabrication process of various printed circuit boards.
The present invention includes a system and method for providing data between a first printed circuit board and a second printed circuit board. The system includes a driving integrated circuit in electrical connection with the first printed circuit board, the driving integrated circuit having a data port and a clock port. A receiving circuit is in electrical connection with the second printed circuit board data capture. A memory device, such as a flip-flop or latch for example, is in electrical connection with the receiving integrated circuit, wherein the memory device has a data input port and a clock input port. An interconnect cable electrically connects the first printed circuit board to the second printed circuit board. The interconnect cable includes at least one data line electrically connecting the first port of the first printed circuit board with the first port of the second printed circuit board for transmitting a data signal. The data line has a predetermined length. The interconnect cable also includes at least one clock line electrically connecting the second port of the first printed circuit board with the second port of the second printed circuit board for transmitting a clock signal associated with a corresponding data signal. The clock line has a length which is greater than the length of the data line such that a time delay is introduced into the clock signal passing between the first and second printed circuit boards.
In one embodiment, the system further includes a first data interconnect electrically connecting the data port of the driving integrated circuit to a first port of the first printed circuit board, while a first clock interconnect electrically connects the clock port of the driving integrated circuit to a second port of the first printed circuit board. Similarly, a second data interconnect electrically connects a first port of the second printed circuit board with the data port of the memory device, while a second clock interconnect electrically connects a second port of the second printed circuit board with the clock port of the memory device.
In another embodiment, the data capture memory device is a latch, while in yet another embodiment, the memory device is a flip-flop. Further, in one embodiment, the first data interconnect and the first clock interconnect have substantially equal lengths. Similarly, the second data interconnect and a second clock interconnect have substantially equal lengths, thereby preventing signal mismatch due to line impedance in these interconnects.
In another embodiment, the memory device is a rising edge sensitive clocking memory device which captures the data signal corresponding to a rising edge of a clock signal. In yet another embodiment the memory device is a falling edge sensitive clocking memory device which captures a data signal corresponding to a falling edge of the clock signal. In either embodiment, the delay time introduced into the clock signal ensures that the memory device captures and holds a stable data signal, as opposed to a transitioning data signal.
The method of the present invention includes transmitting a synchronized data signal and an associated clock signal to a data port and a clock port, respectively, of a first printed circuit board. The data signal is transmitted to a data port of the second printed circuit board via a data line of an interconnect cable, the data line having a predetermined length. A time delay is introduced into the clock signal during transmission of the clock signal to a clock port of a second printed circuit board, thereby creating a delayed clock signal. The clock signal transmitted between the first and second printed circuit board via a clock line of the interconnect cable. The clock line also has a predetermined length, which is greater than the predetermined length of the data line. The data signal and the delayed clock signal is transmitted to a data port and a clock port, respectively, of a memory device in electrical connection with the second printed circuit board. A stable data signal is captured and held within the memory device when an associated delay clock signal changes states at the clock port of the memory device.
In one embodiment, the stable data signal is captured within a rising edge sensitive clocking memory device corresponding to a rising edge of the associated delay clock signal at the clock port of the memory device. In another embodiment, the stable data signal is captured within a falling edge sensitive clocking memory device corresponding to a falling edge of the associated delay clock signal at the clock port of the memory device.